1. Field of the Invention
The invention relates to memories, and more particularly to data access of memories.
2. Description of the Prior Art
Before data is written to a memory, a controller of the memory usually scrambles the data with a scrambler, thus making bits 0 and 1 to have a random distribution in the data. The scrambled data is then stored in the memory, thus preventing bits 0 and 1 from massing in a specific segment of the data. For example, a flash memory is classified into a single-level-cell (SLC) flash memory or a multi-level-cell (MLC) flash memory. When data is written to a MLC flash memory, if the data comprises segments comprising massed bits 0 or massed bits 1, an error bit rate of the data is increased. A controller of the MLC flash memory therefore has to scramble the data before the data is written to the MLC flash memory.
The data scrambled by a scrambler, however, has deficiency. A controller usually transmits data to a flash memory via a data bus. When the controller sends a data bit 1 to the flash memory, a voltage level of the data bus is increased to a logic high level. When the controller sends a data bit 0 to the flash memory, the voltage level of the data bus is decreased to a logic low level. Because bits 0 and 1 in scrambled data have randomized distributions, when the controller sends the scrambled data to the memory for storage via the data bus, the voltage level on the data bus frequently oscillates between the logic high level and the logic low level. The data bus therefore requires high power due to the frequent oscillation of voltage levels thereon, thus increasing power consumption of a system. When the system comprising the controller and the memory is a portable device with a battery power supply, the time span in which the system operates under a normal voltage supply is shorten, thus degrading the performance of the system. Thus, a controller which can scramble data with low power consumption is desired.